
Nano Sentinel: An Explainable Deep Learning Framework for Semiconductor Wafer Defect Classification and Inspection Workflow Support | IJCT Volume 13 – Issue 5 | IJCT-V13I5P63
IJCT
International Journal of Computer Techniques
ISSN 2394-2231 · Peer-Reviewed · Open Access
📚 Volume 13, Issue 5
📅 October 21, 2026
📄 Pages 546–553
🔖 ID: IJCT-V13I5P63
Table of Contents
ToggleNano Sentinel: An Explainable Deep Learning Framework for Semiconductor Wafer Defect Classification and Inspection Workflow Support
Author(s)
Prof. Vetrikani R, Ranjith Kumar K.M, Sathvik B Rao, Pranav Aditya R, Rahul Gowda C, Vardhan Kumar R
Abstract
The wafer-map defect pattern classification is an important task in semiconductor manufacturing, as the spatial arrangement of defective dies can provide valuable information for identifying recurring failure patterns. The manual inspection of wafer maps can be extremely labor-intensive, especially if large volumes of inspection data have to be reviewed. Deep-learning methods provide a way to automate the pattern classification, but the classification predictions are only a part of an inspection workflow and do not present evidence for individual predictions. This paper introduces Nano Sentinel, a prototype framework that integrates deep-learning-based wafer-map classification with explainability and inspection workflow elements. The classification component uses MobileNetV2 transfer learning to classify wafer maps from the WM-811K dataset into nine Center, Donut, Edge-Loc, Edge-Ring, Loc, Near-full, Random, Scratch, and none classes. The framework incorporates Gradient-weighted Class Activation Mapping for model visual inspection, maximum softmax probability for confidence reporting, a provisional defect-severity assessment, rule-based inspection recommendations, and inspection record generation. A lot-aware partition was used for training and validation of the model. Preliminary experiments with the selected V2 model achieved 94.56% validation accuracy and 0.8332 macro-averaged F1-score. An independent diagnostic evaluation on the official test partition returned 88.66% accuracy and 0.4727 macro-F1, which suggests significant variance between the performance of different classes and highlights the need for further generalization studies. The workflow components were demonstrated as prototype decision support features, rather than a fully validated industrial inspection system. The study emphasized the combination of classification, visualization, and documentation elements while class imbalance, minority-class mistakes, and the validation of severity and rule-based decisions are important areas of future work.
Keywords
Semiconductor manufacturing, wafer-map defect classification, MobileNetV2, transfer learning, explainable artificial intelligence, Grad-CAM, deep learning, automated inspection, inspection workflow.
Conclusion
Nano Sentinel, an intelligent wafer-map inspection framework, which makes use of a deep-learning-based defect classifier with Grad-CAM visual explanations and inspection workflow support, is introduced. The framework employs the classifier based on the MobileNetV2 architecture to classify defect categories in the wafer maps from the WM-811K dataset into nine classes. The tool also allows presenting the confidence scores, preliminary severity assessment and inspection recommendation, and the PDF report generation. The MobileNetV2 V2 model that yielded the best results achieved the value of 94.56% for the validation accuracy, 0.8332 for the macro-F1 score, and 0.9445 for the weighted-F1 score. For the diagnostic evaluation of the official test partition, the model achieved 88.66% accuracy, 0.4727 macro-F1, and 0.9005 weighted-F1. The significant difference between macro and weighted F1 scores for the test partition illustrates the problem of imbalanced classes and the varying ability of the model to recognize different defect categories. In particular, several minor defect categories were recognized with low performance, which should be addressed by future research. Grad-CAM provides a way to visually assess what parts of the input contributed to the model’s decision, which can be used to increase the understanding of the model. However, such an approach cannot verify that the model did not make an error, and the diagnostic evaluation showed that achieving high confidence across all classes is challenging. Thus, the current prototype should be regarded as a research tool that requires further validation before it can be applied as an industrial inspection system.
References
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[2]T. Nakazawa and D. V. Kulkarni, “Wafer map defect pattern classification and image retrieval using convolutional neural network,” IEEE Trans. Semicond. Manuf., vol. 31, no. 2, pp. 309–314, May 2018.
[3]K. Kyeong and H. Kim, “Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks,” IEEE Trans. Semicond. Manuf., vol. 31, no. 3, pp. 395–402, Aug. 2018, doi: 10.1109/TSM.2018.2841416.
[4]M. Saqlain, B. Jargalsaikhan, and J. Y. Lee, “A voting ensemble classifier for wafer map defect patterns identification in semiconductor manufacturing,” IEEE Trans. Semicond. Manuf., vol. 32, no. 2, pp. 171– 182, May 2019.
[5]M. Piao, C. H. Jin, J. Y. Lee, and J.-Y. Byun, “Decision tree ensemblebased wafer map failure pattern recognition based on Radon transformbased features,” IEEE Trans. Semicond. Manuf., vol. 31, no. 2, pp. 250– 257, May 2018.
[6]J. Wang, C. Xu, Z. Yang, J. Zhang, and X. Li, “Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition,” IEEE Trans. Semicond. Manuf., vol. 33, no. 4, pp. 587–596, Nov. 2020.
[7]M. Sandler, A. Howard, M. Zhu, A. Zhmoginov, and L.-C. Chen, “MobileNetV2: Inverted residuals and linear bottlenecks,” in Proc. IEEE/CVF Conf. Comput. Vis. Pattern Recognit. (CVPR), 2018, pp. 4510– 4520, doi: 10.1109/CVPR.2018.00474.
[8]S. J. Pan and Q. Yang, “A survey on transfer learning,” IEEE Trans. Knowl. Data Eng., vol. 22, no. 10, pp. 1345–1359, Oct. 2010, doi: 10.1109/TKDE.2009.191.
[9]R. R. Selvaraju, M. Cogswell, A. Das, R. Vedantam, D. Parikh, and D. Batra, “Grad-CAM: Visual explanations from deep networks via gradientbased localization,” in Proc. IEEE Int. Conf. Comput. Vis. (ICCV), 2017, pp. 618–626, doi: 10.1109/ICCV.2017.74.
[10]A. Adadi and M. Berrada, “Peeking inside the black-box: A survey on explainable artificial intelligence (XAI),” IEEE Access, vol. 6, pp. 52138– 52160, 2018, doi: 10.1109/ACCESS.2018.2870052.
[11]J. Adebayo, J. Gilmer, M. Muelly, I. Goodfellow, M. Hardt, and B. Kim, “Sanity checks for saliency maps,” in Adv. Neural Inf. Process. Syst. (NeurIPS), vol. 31, 2018, pp. 9505–9515.
📋 How to Cite This Paper
Prof. Vetrikani R, Ranjith Kumar K.M, Sathvik B Rao, Pranav Aditya R, Rahul Gowda C, Vardhan Kumar R (2026). Nano Sentinel: An Explainable Deep Learning Framework for Semiconductor Wafer Defect Classification and Inspection Workflow Support. International Journal of Computer Techniques, 13(5), 546–553. ISSN: 2394-2231. DOI: https://doi.org/10.5281/zenodo.23539976
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